1. Field of the Invention
The present invention relates to a semiconductor memory device capable of electrically erasing and writing information and a manufacturing method of the same, and in particular, to a device and a method for preventing possible deterioration of an endurance characteristic during an erasing operation of data as well as possible drain disturb phenomenon during a writing operation of data.
2. Description of the Background Art
As one of nonvolatile semiconductor memory devices, there has been known an EEPROM (Electrically Erasable and Programmable Read Only Memory) capable of freely programming data and capable of electrically writing and erasing data. Although the EEPROM has an advantage that both the writing and erasing operations can be executed electrically, it disadvantageously requires two transistors for each memory cell, and therefore integration to a higher degree is difficult. For this reason, there has been proposed a flash EEPROM including memory cells, each of which is formed of one transistor, and allowing electrical batch-erasing of written electric information charges, for example, in U.S. Pat. No. 4,868,619.
FIG. 57 is a block diagram showing a general structure of a flash EEPROM in the prior art. Referring to FIG. 57, the flash EEPROM includes a memory cell matrix 100, an X-address decoder 200, a Y-gate sense amplifier 300, a Y-address decoder 400, an address buffer 500, an I/O (input/output) buffer 600 and a control logic 700.
The memory cell matrix 100 includes a plurality of memory cells arranged in rows and columns. The X-address decoder 200 and Y-gate sense amplifier 300 are connected to the memory cell matrix 100 for selecting the rows and columns thereof. The Y-address decoder 400 is connected to the Y-gate sense amplifier 300 for amplifying selection information of column. The address buffer 500 is connected to the X-address decoder 200 and Y-address decoder 400, and temporarily stores the address information.
The Y-gate sense amplifier 300 is connected to the I/O buffer 600 for temporarily storing I/O data. The control logic 700 is connected to the address buffer 500 and I/O buffer 600 for controlling an operation of the EEPROM. The control logic 700 carries out the control based on a chip enable signal (/CE), an output enable signal (/OE) and a program signal (/PGM).
FIG. 58 is an equivalent circuit diagram showing a schematic structure of the memory cell matrix 100 shown in FIG. 57. Referring to FIG. 58, the memory cell matrix 100 includes a plurality of word lines WL.sub.1, WL.sub.2, . . . , WL.sub.i extending in a row direction and a plurality of bit lines BL.sub.1, BL.sub.2, . . . , BL.sub.i extending in a column direction and perpendicularly crossing the word lines. At crossings of the word lines and bit lines, there are disposed memory transistors Q.sub.11, Q.sub.12, . . . , Q.sub.ii each having a floating gate electrode, respectively. Each memory transistor has a drain connected to the corresponding bit line, and a control gate electrode connected to the corresponding word line. A source of each memory transistor is connected to corresponding one of the source lines SL.sub.1, SL.sub.2 . . . , SL.sub.i. The source lines SL.sub.1, SL.sub.2, . . . , SL.sub.i are connected to source lines S.sub.1 and S.sub.2 disposed at opposite sides.
FIG. 59 is a schematic plan showing a flash EEPROM of a stacked gate type (multilayered gate type) of the prior art. FIG. 60 is a cross section taken along line A--A in FIG. 59. Referring to FIGS. 59 and 60, a structure of the flash EEPROM in the prior art will be described below.
Referring to FIG. 59, control gate electrodes 137 are mutually connected to form word lines in a lateral direction (row direction). Bit lines 139 extend perpendicularly to the word lines 137. Each bit line 139 connects drain diffusion regions 132, which are aligned in a longitudinal direction (column direction), to each other. The bit lines 139 are electrically connected to the drain diffusion regions 132 through drain contacts 140. Referring to FIG. 60, the bit line 139 is formed extending over a smooth coat film 141. Referring to FIG. 59 again, source diffusion regions 133 are formed in regions which extend along the word lines 137 and are located between the word lines 137 and element isolating oxide films 130. Each drain diffusion region 132 is formed in a region between the word line 137 and element isolating oxide film 130.
Referring to FIG. 60, on a main surface of a P-type silicon substrate 131, there are formed the drain diffusion regions 132 and source diffusion regions 133 at opposite sides of channel regions with predetermined spaces between each other. On the channel regions, there are formed floating gate electrodes 135 with a thin oxide film 134 of about 100 .ANG. in thickness therebetween. The control gate electrode 137 is formed on each floating gate electrode 135 with an interlayer insulating film 136 therebetween for electrically isolating them from each other. The floating gate electrode 135 and control gate electrode 137 are formed of polysilicon layers. A thermal oxide film 138 is formed by thermal oxidation of surfaces of the P-type silicon substrate 131, floating gate electrode 135 made of polysilicon layer and control gate electrode 137. The floating gate electrode 135 and control gate electrode 137 are covered with the smooth coat film 141 formed of an oxide film or the like.
An operation of the flash EEPROM will be described below with reference to FIG. 60.
In writing operation, a voltage V.sub.D1 of about 6 to 8 V is applied to the drain diffusion region 132, and a voltage V.sub.G1 of about 10 to 15 V is applied to the control gate electrode 137. The voltages V.sub.D1 and V.sub.G1 thus applied generate an avalanche breakdown phenomenon at the vicinity of the drain diffusion region 132 and oxide film 134. The avalanche breakdown phenomenon generates electrons having high energy. A part of the electrons are attracted and implanted into the floating gate 135 by an electric field caused by the voltage V.sub.G1 applied to the control gate electrode 137. The electrons thus accumulated in the floating gate electrode 135 increases a threshold voltage V.sub.TH of the control gate transistor. The state where the threshold voltage V.sub.TH is higher than a predetermined value is a written state and is also referred to as a state of "0".
In an erasing operation, a voltage V.sub.S of about 10 to 12 V is applied to the source diffusion region 133. The control gate electrode 137 is maintained at the ground voltage, and the drain diffusion region 133 is maintained at the floating state. The electric field generated by the voltage V.sub.S applied to the source diffusion region 133 causes the electrons in the floating gate electrode 135 to pass through the thin oxide film 134 by virtue of an F-N (Fowler-Nordheim) tunneling phenomenon. Owing to the draw of electrons in the floating gate electrode 135 in this manner, the threshold voltage V.sub.TH of the control gate transistor decreases. This state where the threshold voltage V.sub.TH is lower than the predetermined value is an erased state, and is also referred to as a state of "1". Since the sources of transistors are mutually connected as shown in FIG. 59, batch erasing of all the memories is carried out by this erasing operation.
In reading operation, a voltage V.sub.G2 of about 5 V is applied to the control gate electrode 137, and a voltage V.sub.D2 of about 1 to 2 V is applied to the drain diffusion region 132. In this operation, the determination of "1" or "0" described above is carried out based on whether a current flows through the channel region of the control gate transistor or not, i.e., whether the control gate transistor is in the on-state or off-state. Thereby, information is read.
The conventional semiconductor memory device described above suffers from the drain disturb phenomenon caused in the data writing operation, as will be described below. FIG. 61 is a partial equivalent circuit diagram of a memory cell matrix 100 showing the drain disturb phenomenon. FIG. 62 is a cross section showing the drain disturb phenomenon caused by the F-N tunneling. FIG. 63 is a cross section showing the drain disturb phenomenon caused by interband tunneling.
Referring to FIG. 61, the flash EEPROM in the prior art includes the memory cells, each of which is formed of one transistor, and thus does not include a selection transistor, which is employed in a conventional EEPROM. Therefore, in the operation for Writing information, the write voltage of 6 to 8 V is applied to the drain diffusion regions (D) of all the memory transistors connected to the same bit lines (BL.sub.1). More specifically, the cell selected for writing information receives at its drain diffusion region (D) the voltage of 6 to 8 V through the bit line BL.sub.1, and also receives at its control gate electrode (C) the voltage of 10 to 15 V through the word line WL.sub.1. During this application of voltages, the voltage of 6 to 8 V is applied to the drain diffusion regions (D) of unselected cells through the bit line BL.sub.1. The unselected cells receiving at their drain diffusion regions (D) the voltage of 6 to 8 V also receives at their control gate electrodes (C) the voltage of 0 V. When the unselected cell is in the written state, electrons have been accumulated in the floating gate electrode of the unselected cell, and thus the floating gate electrode is maintained at a potential of about -3 V. When the unselected cell maintained in this state receives the voltage of 6 to 8 V and the voltage of 0 V (unselected state) at its drain diffusion region (D) and control gate electrode (C), respectively, a high electric field, which may attain 10 MV/cm, generates between the floating gate electrode and drain diffusion region. Thereby, the drain disturb phenomena occurs due to the F-N tunneling and interband tunneling.
Referring to FIG. 62, when the high electric field attaining 10 MV/cm is generated between the floating gate electrode 135 and drain diffusion region 132, electrons implanted into the floating gate electrode 135 are drawn to the drain diffusion region 132 due to the F-N tunneling. This results in undesired erasing in the unselected cell. This is a so-called "drain disturb phenomenon" by the F-N tunneling.
Referring to FIG. 63, the high electric field generated between the floating gate electrode 135 and drain diffusion region 132 causes the interband tunneling, which generates holes. The holes thus generated are implanted into the floating gate electrode 135, resulting in the same state as that where electrons are drawn. Consequently, contents in the unselected cell are erased. This is the drain disturb phenomenon by the interband tunneling.
The drain disturb phenomenon causes destruction of written data in a certain probability, resulting in reduction of reliability of elements.
The conventional flash EEPROM further suffers from a problem that an endurance characteristic may deteriorate in a data erasing operation, as will be described below. FIG. 64 is a cross section showing deterioration of the endurance characteristic which is caused in the data erasing operation. Referring to FIG. 64, in the erasing operation of the conventional flash EEPROM, the control gate electrode 137 receives a voltage of 0 V, and the source diffusion region 133 receives a voltage of about 10 to 12 V. During this operation, the interband tunneling occurs at the vicinity of source diffusion regions 133, and thus holes are generated. The holes thus generated are trapped by the oxide film 134 located under the floating gate electrode 135, resulting in deterioration of the film property of oxide film 134. The deterioration of film property of oxide film 134 impedes the draw of electron from the floating gate electrode 135 in the data erasing operation. This phenomenon is referred to as "deterioration of the endurance characteristic", and is disclosed, e.g., in IEEE ELECTRON DEVICE LETTERS, Vol. 10, No. 3, March 1989, pp. 117-119. Further, in the conventional flash EEPROM, the source of each memory cell transistor is connected to the source lines SL.sub.1, SL.sub.2, . . . , as shown in FIG. 58. In the prior art, the source diffusion regions 133 are used as the source lines SL.sub.1, SL.sub.2, . . . . In other words, the source diffusion regions 133 are formed to be common to the plurality of memory cell transistors for forming the source lines SL.sub.1, SL.sub.2, . . . .
However, the source lines SL.sub.1, SL.sub.2, . . . thus formed by the source diffusion regions 133 cause a disadvantage that the source lines SL.sub.1, SL.sub.2, . . . have a large resistance in the case where the size of source diffusion region 133 is reduced in accordance with miniaturization. This results in delay of data signals.
As described above, the conventional flash EEPROM suffers from generation of the drain disturb phenomenon in the data writing operation, and also suffers from deterioration of the endurance characteristic in the data erasing operation. Further, miniaturization of elements unpreferably increases resistances of the source diffusion regions 133 forming the source lines SL.sub.1, SL.sub.2, . . . .